#### Definition:

*A nine-value resolved logic type Std_logic is not a part of the VHDL Standard. It is defined in IEEE Std 1164.*

#### Syntax:

**type** std_ulogic **is **( 'U', -- Uninitialized

'X', -- Forcing Unknown

'0', -- Forcing 0

'1', -- Forcing 1

'Z', -- High Impedance

'W', -- Weak Unknown

'L', -- Weak 0

'H', -- Weak 1

'-' -- Don't Care

);

**type** std_ulogic_vector **is array** (natural **range** <> ) **of** std_ulogic;

**function** resolved (s : std_ulogic_vector ) **return** std_ulogic;

**subtype** std_logic **is** resolved std_ulogic;

#### Description

The Std_ulogic type is an extension of the standard Bit type. It defines nine values, which allow specifying logical systems. Like Bit, this type is not resolved, i.e. it is not allowed to specify two value assignments to a signal of the Std_ulogic type.

In order to facilitate specification of multiple-driven signals (like data buses) the Std_Logic_1164 package defines resolution function for Std_ulogic, which in turn serves as a basis for declaration of Std_Logic type.

The Std_Logic_1164 package defines overloaded logical operators ("and", "nand", "or", "nor", "xor", and "not") for operands of the Std_ulogic type. Moreover, two conversion functions are defined as well: Std_ulogic to Bit (function ** To_Bit**), and Bit to Std_ulogic (function

**).**

*To_StdULogic*#### Examples

Example 1

**Signal** FlagC : Std_Logic := 'Z';

ALU : **process****begin**

. . .** if** Carry **then** FlagC <= '1'; **end** **if**;**end** **process** ALU;

Comm : **process****begin**

. . .

FlagC <= '0';**end** **process** Comm;

Std_Logic is a resolved type, which means that multiple assignments to the same object are legal. If FlagC was of the Std_Ulogic type, such a code would not be acceptable.

#### Important Notes

· Std_Logic is defined as a subtype of Std_ULogic, therefore all operators and functions defined for Std_Ulogic can be applied to Std_Logic.

· Std_Logic is the industry standard logic type and in practice majority of signals are of this type (or its vector derivative, Std_Logic_Vector type).

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